The ESP32-S3 is the chip most new camera, display, and AI-adjacent ESP32 projects are built on now -- it's what replaced the aging ESP32-CAM's underlying silicon in most new camera boards, and it's the go-to choice any time a project needs native USB, more RAM for a display buffer, or just more GPIO than a classic ESP32 devkit gives you. If a project idea starts with "I need a camera and WiFi" or "I want this to show up as a USB device," the S3 is very likely the right chip before looking anywhere else.
It keeps the classic ESP32's dual-core design -- two Xtensa LX7 cores at up to 240MHz -- but adds native USB (no separate USB-to-serial chip needed on some boards), vector instructions aimed at machine-learning workloads, and support for external PSRAM for projects that need more working memory than the chip's internal SRAM alone provides.
This guide covers a typical ESP32-S3 DevKitC-1 layout, the reference design most third-party S3 boards follow -- GPIO, ADC, PWM, native USB, the radio set, and the exact strapping pins worth knowing before committing a design to this chip.
GPIO Pins and Numbering
The S3 has the largest GPIO budget in the mainstream ESP32 lineup -- up to 45 physical GPIOs on the chip (GPIO0-21 and GPIO26-48, with a gap in between), though a specific devkit typically breaks out somewhere in the 35-45 range once a handful of flash/PSRAM-connected pins are set aside.
pinMode(4, OUTPUT);
digitalWrite(4, HIGH);
Strapping Pins -- The Exact List
Per Espressif's datasheet, the ESP32-S3 has four strapping pins: GPIO0, GPIO3, GPIO45, and GPIO46. GPIO0 carries the primary boot-mode role familiar from the classic ESP32 -- held low at power-on, it forces the chip into download/flashing mode, which is exactly why GPIO0 is the pin wired to the BOOT button on essentially every S3 devkit. GPIO46 additionally influences ROM message printing, while GPIO3 and GPIO45 configure the voltage the chip expects on certain internal power domains -- get these wrong on a custom board (rather than a reference devkit, which handles it correctly by design) and the chip can fail to boot or run flash access at the wrong voltage entirely.
PSRAM and Flash-Connected Pins
On modules with octal PSRAM (common on S3 boards aimed at camera or display use), GPIO35 through GPIO37 are typically committed internally and don't reach the header. Boards without PSRAM, or with quad PSRAM instead, free up a few more usable pins -- check your specific module's variant before assuming a pin is free. GPIO26 through GPIO32 are commonly tied to onboard SPI flash and are similarly off-limits for general use.
ADC Pins
The S3 has two 12-bit ADCs (ADC1 on GPIO1-10, ADC2 on GPIO11-20), spread across up to 20 GPIOs combined -- a substantial analog budget, closer to the classic ESP32's than the C3's or C6's smaller single-ADC arrangement.
int reading = analogRead(1); // GPIO1, ADC1 channel
As on the classic ESP32, ADC2 pins can become unreliable while WiFi is actively transmitting, since the radio and ADC2 share internal hardware resources. For analog readings that need to stay reliable with WiFi connected, stick to ADC1 pins (GPIO1-10) rather than ADC2 (GPIO11-20).
PWM
Fully software-mapped via the LEDC peripheral to essentially any GPIO, with up to eight independent PWM channels active simultaneously.
ledcAttach(4, 5000, 8);
ledcWrite(4, 128); // ~50% duty cycle
Native USB
This is a genuine S3-specific feature worth calling out separately: the chip has a built-in USB OTG peripheral, wired on most boards to GPIO19 (D-) and GPIO20 (D+). Some S3 boards use this for direct USB communication -- appearing as a USB HID device, mass storage, or CDC-serial without a separate USB-to-UART bridge chip -- while others still include a traditional USB-serial chip for simplicity, with USB only reaching the UART bridge rather than the S3's native peripheral directly. Check which your specific board uses before assuming native USB behavior; the two setups look identical from the outside but behave very differently in firmware.
I2C, SPI, and UART
I2C: Software-mapped to any two free GPIOs via Wire.begin(sda, scl), commonly defaulting to GPIO8/GPIO9 on many S3 devkits.
Wire.begin(8, 9); // SDA, SCL — adjust to your board's free pins
SPI: The S3 has multiple SPI peripherals, with one commonly dedicated to onboard flash/PSRAM and the rest free for external displays, SD cards, or other SPI peripherals -- SPI.begin(sck, miso, mosi, cs) assigns any free set.
UART: Multiple hardware UARTs are available. On boards without native-USB serial, one is typically tied to a USB-to-UART chip for flashing and debugging; the rest are free for GPS modules, other microcontrollers, or additional debug consoles.
Camera Interface (on Camera-Equipped Boards)
S3-based camera boards (the common successor to the original ESP32-CAM) wire a set of GPIOs internally to a camera ribbon connector, consuming a chunk of the chip's GPIO budget before any external peripheral gets a look-in -- the same trade-off the ESP32-CAM makes, just with more total pins available on the S3 to spare afterward. The exact GPIOs used vary by board (AI-Thinker-style modules, Freenove, and others each use different camera pin mappings), so check the specific CAMERA_MODEL_ definition for your board rather than assuming a universal mapping.
Wireless: WiFi 4 and BLE 5.0
Same radio generation as the C3 -- 2.4GHz WiFi (802.11 b/g/n) and BLE 5.0, no WiFi 6 and no 802.15.4. The S3's strengths are elsewhere (USB, GPIO count, PSRAM, ML acceleration), not in the radio department -- a project needing WiFi 6 or Thread/Zigbee alongside camera or display work would need to pair an S3 with a separate C6 or H2, since no single current Espressif chip combines both feature sets.
Power Pins
| Pin | Function | Notes |
|---|---|---|
| 5V / VIN | Power input | Via USB or an external 5V supply |
| 3V3 | Regulated 3.3V output | Powers the chip and any 3.3V peripherals |
| GND | Ground | Multiple ground pins on most devkits |
3.3V logic throughout. Level-shift any 5V sensor before wiring it to a GPIO.
How the S3 Compares to Its Siblings
| Chip | Cores | GPIO (typical devkit) | ADC pins | Native USB | Best for |
|---|---|---|---|---|---|
| ESP32-C3 | Single RISC-V | ~16-19 | 5 | No | Cheapest general WiFi/BLE sensor node |
| ESP32-S3 | Dual Xtensa LX7 | ~35-45 | ~20 | Yes | Camera, display, USB, AI-adjacent work |
| ESP32-C6 | RISC-V + LP core | ~22-23 | 7 | No | Matter, Thread, Zigbee alongside WiFi |
| Classic ESP32 | Dual Xtensa LX6 | ~30-34 | ~18 | No | Legacy projects, well-documented reference designs |
The S3 is the clear pick whenever GPIO count, RAM, or native USB matters more than radio variety -- if a project's bottleneck is "I'm running out of pins" or "I need this to plug into a computer as a USB device," the S3 solves both in a way none of its RISC-V siblings currently can.
Which Projects the S3 Actually Fits
A strong fit: ESP32-CAM-style camera projects, anything driving a display that benefits from extra RAM via PSRAM, USB-HID or USB-MIDI devices, and any project that's simply running out of GPIO on a smaller chip.
A weaker fit: projects needing Zigbee, Thread, or WiFi 6 (none of which the S3 has), or extremely cost-sensitive designs where a C3 would do the same job for less.
Common Mistakes and How to Avoid Them
Assuming every S3 board has native USB wired the same way. Some use it, some still use a separate USB-serial chip -- check before writing USB-HID or USB-CDC code against GPIO19/20.
Wiring a peripheral to GPIO35-37 on a PSRAM-equipped board. These are internally committed on octal-PSRAM modules and won't behave like a free GPIO.
Reading an analog sensor on ADC2 (GPIO11-20) while WiFi is active. Same ADC2/radio conflict as the classic ESP32 -- move the sensor to an ADC1 pin (GPIO1-10) if WiFi needs to stay connected.
Assuming a universal camera pinout. Different S3 camera board vendors wire the ribbon connector to different GPIOs -- match the CAMERA_MODEL_ definition to your specific board.
Wiring anything to GPIO0, 3, 45, or 46 without checking the strapping role first. These four pins configure boot mode and internal voltage settings -- an external circuit that pulls one into an unexpected state at power-up is a common cause of boot failures on custom S3 boards.
Practical Pin Usage Tips
Confirm your specific module's PSRAM and flash configuration before planning a pinout. The S3 ships in quad-flash, quad-PSRAM, and octal-PSRAM variants, and each reserves a different number of GPIOs internally -- a pin that's free on one module variant may be committed on another.
Use ADC1 pins for anything that needs to stay accurate with WiFi connected. ADC2 sharing hardware with the radio is a carryover from the classic ESP32, and it's an easy trap to fall into on the S3 since the chip otherwise feels like a strict upgrade.
Take advantage of the larger GPIO budget to keep buses separate. With up to 45 pins on the chip, there's rarely a real need to share a bus between unrelated peripherals the way a pin-starved board like an ESP32-CAM forces -- give a display its own SPI bus and a sensor cluster its own I2C bus rather than daisy-chaining everything through the same few pins out of habit.
Check whether your board exposes native USB or a USB-serial bridge before writing USB-HID code. Code that opens the chip's native USB peripheral directly will do nothing useful on a board that only wires up a traditional USB-to-UART chip.
Leave headroom for PSRAM-hungry libraries. Camera capture buffers, display frame buffers, and TensorFlow Lite Micro models can all eat through internal SRAM fast -- if a project uses any of these, budget for external PSRAM from the start rather than discovering the ceiling mid-project.
Summary: ESP32-S3 Pin Reference at a Glance
ESP32-S3 · Dual-core Xtensa LX7 @ up to 240MHz · 512KB SRAM + optional external PSRAM · WiFi 4 · BLE 5.0 · Up to 45 GPIO on the chip, 35-45 typical on a devkit · Strapping pins: GPIO0, 3, 45, 46 · 2x 12-bit ADC (GPIO1-10, GPIO11-20) · Native USB OTG on GPIO19/20
Popular ESP32-S3 Boards and Where This Guide Applies
The GPIO layout described here matches Espressif's own DevKitC-1 reference design, which the majority of third-party S3 boards follow closely -- including popular general-purpose boards from Freenove and LILYGO, and most current-generation ESP32-S3 camera boards that replaced the older AI-Thinker ESP32-CAM design. Camera-specific boards deviate the most from a plain DevKitC-1 pinout, since a meaningful chunk of GPIO gets committed internally to the camera ribbon connector before a project ever wires up an external peripheral -- always cross-reference the specific board's own schematic or the matching CAMERA_MODEL_ definition in the ESP32 camera library rather than assuming a generic S3 pinout applies unmodified.
Display-focused S3 boards (driving a touchscreen over SPI or a parallel RGB interface) are the other common variant worth flagging -- these frequently claim a large contiguous block of GPIOs for the display bus alone, on top of whatever the board's PSRAM configuration already reserves. On a board like this, it's worth checking the vendor's example code for which pins remain genuinely free before planning any additional peripherals.
Quick Answers to Common ESP32-S3 Pin Questions
Why did my project's camera board switch from ESP32-CAM to an S3 variant? More GPIO headroom, more RAM via PSRAM, and native USB -- the S3 solves the classic ESP32-CAM's biggest complaint, which was running out of free pins the moment the camera and SD card claimed their share.
Does the S3 support 5GHz WiFi or Thread/Zigbee? No -- same radio generation as the C3, 2.4GHz WiFi 4 and BLE 5.0 only. For those radios, the C6 or H2 is the right chip.
Which exact pins are the strapping pins? GPIO0, GPIO3, GPIO45, and GPIO46 -- with GPIO0 carrying the primary boot-mode role, same concept as the classic ESP32's GPIO0.
Why is GPIO35-37 unavailable on my board? Those pins are wired internally to octal PSRAM on boards that include it -- normal, not a wiring mistake.
Can I use the S3 for machine-learning inference? Yes, within reason -- it has vector instructions and enough RAM (especially with external PSRAM) for small models like wake-word detection or basic image classification, though it's not a substitute for a dedicated AI accelerator on heavier workloads.
Can I use 5V sensors directly? No -- 3.3V logic throughout.
Where to Go From Here
Once the PSRAM-reserved pins and the ADC1/ADC2 WiFi conflict feel familiar, the native USB peripheral is worth exploring next for anything that wants to appear as a USB HID device or drive without a separate serial chip in the loop. From there, the compact XIAO ESP32-S3 is worth a look for anything space-constrained that still wants this chip's GPIO and RAM headroom, and if a project ever needs Thread or Zigbee alongside the S3's camera and display strengths, pairing it with a dedicated ESP32-H2 covers that gap without waiting for a single chip that does both.